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Description Features
HM538253B Series HM538254B Series
2 M VRAM (256-kword x 8-bit) Hyper Page Mode (HM538254B)
The HM538253B/HM538254B is a 2-Mbit multiport video RAM equipped with a 256-kword x 8-bit dynamic RAM and a 512-word x 8-bit SAM (full-sized SAM). Its RAM and SAM operate independently and asynchronously. The HM538253B/HM538254B is upwardly compatible with the HM534253B/HM538123B except that the pseudo-write-transfer cycle is replaced with masked-write-transfer cycle, which has been approved by JEDEC. Furthermore, several new features have been added to the HM538253B/HM538254B which do not conflict with the conventional features. The stopping column feature realizes allows greater flexibility for split SAM register lengths. Persistent mask is also installed according to the TMS34020 features. The HM538254B has Hyper page mode which enables fast page cycle.
* Multiport organization:RAM and SAM can operate asynchronously and simultaneously: RAM: 256-kword x 8-bit SAM: 512-word x 8-bit * Access time RAM: 70 ns/80 ns/100 ns max SAM: 20 ns/23 ns/25 ns max * Cycle time RAM: 130 ns/150 ns/180 ns min SAM: 25 ns/28 ns/30 ns min * Low power Active RAM: 605 mW/550 mW/495 mW SAM: 358 mW/330 mW/303 mW Standby 38.5 mW max * Masked-write-transfer cycle capability * Stopping column feature capability * Persistent mask capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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E0163H10 (Ver. 1.0) (Previous ADE-203-264A/265 (Z)) Jul. 6, 2001 (K)
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HM538253B/HM538254B Series
* Fast page mode capability (HM538253B) Cycle time: 45 ns/50 ns/55 ns Power RAM: 605 mW/578 mW/550 mW * Hyper page mode capability (HM538254B) Cycle time: 35 ns/40 ns/45 ns Power RAM: 715 mW/660 mW/605 mW * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Split transfer cycle capability * Block write mode capability * Flash write mode capability * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible
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Type No. HM538253BJ-7 HM538253BJ-8 HM538253BJ-10 HM538254BJ-7 HM538254BJ-8 HM538254BJ-10 HM538253BTT-7 HM538253BTT-8 HM538253BTT-10 HM538254BTT-7 HM538254BTT-8 HM538254BTT-10 2
Ordering Information
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Access Time 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns
Data Sheet E0163H10
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Package
400-mil, 40-pin plastic SOJ (CP-40D)
44-pin thin small outline package (TTP-44/40DA)
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HM538253B/HM538254B Series
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VCC SC SI/O0 SI/O1 SI/O2 SI/O3 DT/OE I/O0 I/O1 I/O2 I/O3 VSS WE RAS A8 A7 A6 A5 A4 VCC
Pin Arrangement
HM538253BJ Series HM538254BJ Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V SS SI/O7 SI/O6 SI/O5 SI/O4 SE I/O7 I/O6 I/O5 I/O4 VSS DSF1 NC CAS QSF A0 A1 A2 A3 V SS VCC SC SI/O0 SI/O1 SI/O2 SI/O3 DT/OE I/O0 I/O1 I/O2 NL NL I/O3 VSS WE RAS A8 A7 A6 A5 A4 VCC HM538253BTT Series HM538254BTT Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 V SS SI/O7 SI/O6 SI/O5 SI/O4 SE I/O7 I/O6 I/O5 I/O4 NL NL VSS DSF1 NC CAS QSF A0 A1 A2 A3 V SS
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(Top view)
Data Sheet E0163H10 3
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HM538253B/HM538254B Series
Pin Description
Pin Name A0-A8
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I/O0-I/O7 SI/O0-SI/O7 RAS CAS WE DT/OE SC SE DSF1 QSF VCC VSS NL NC 4
Function Address inputs
RAM port data inputs/outputs
SAM port data inputs/outputs
Row address strobe Column address strobe Write enable
Data transfer/output enable Serial clock
SAM port enable
Special function input flag
Special function output flag Power supply Ground
No lead
No connection
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Data Sheet E0163H10
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HM538253B/HM538254B Series
Sense Amplifier & I/O Bus
Block Write Flash Write Control Control
511
0
Input Data Control Address Mask Register
Transfer Gate Data Register
Serial Output Buffer
Serial Input Buffer
Mask Register
Color Resister
SI/O0 - SI/O7
Input Buffer
Output Buffer
Timing Generator
I/O0 - I/O7
Data Sheet E0163H10 5
RAS CAS DT/OE WE DSF1 SC SE
SAM Column Decoder
Column Decoder
Transfer Gate
Data Register
SAM I/O Bus
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Block Diagram
A0 - A8 A0 - A8 Row Address Buffer
A0 - A8 Column Address Buffer
Refresh Counter
Row Decoder
Serial Address Counter
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QSF
0 511 Memory Array
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HM538253B/HM538254B Series
Pin Functions
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RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of R A S. The input level of these signals determines the operation cycle of the HM538253B/HM538254B. CAS (input pin): Column address and DSF1 signals are fetched into the chip at the falling edge of CAS, which determines the operation mode of the HM538253B/HM538254B. A0-A8 (input pins): Row address (AX0-AX8) is determined by A0-A8 level at the falling edge of RAS. Column address (AY0-AY8) is determined by A0-A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with the SAM data register, and column address is the SAM start address after transfer.
WE: The WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM538253B/ HM538254B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of RAS, no mask write cycle is executed. After that, WE switches to read/write cycles. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). I/O0-I/O7 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins is masked and internal data is retained. After that, they function as input/output pins as those of a standard DRAM. In block write cycle, the data functions as column mask data at the falling edges of CAS and WE. DT/OE (input pin): The DT/OE pin functions as a DT (data transfer) pin at the falling edge of RAS and as an OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because the internal pointer is incremented at the rising edge of SC. SI/O0-SI/O7 (input/output pins): SI/Os are SAM input/output pins. I/O direction is determined by the previous transfer cycle. If it was a read transfer cycle, SI/O outputs data. If it was a masked write transfer cycle, SI/O inputs data. DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS when new functions such as color register and mask register read/write, split transfer, and flash write, are used.
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Data Sheet E0163H10
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HM538253B/HM538254B Series
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Table 1
RAS Mnemonic Code CBRS CBRR CBRN MWT MSWT RT SRT RWM BWM RW (No) BW (No) FWM 0 0 0 1 1 1 1 1 1 1 1 1 LMR and 1 Old Mask Set LCR Option 1 0
DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all operations of the HM538253B/HM538254B. QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing address 255 in SAM, and from high to low by accessing address 511 in SAM. Operation Cycles of the HM538253B/HM538254B
CAS Address CAS -- -- -- TAP TAP TAP TAP I/On Input RAS -- -- -- WM WM -- -- CAS/WE -- -- -- -- -- -- -- Input data Column Mask Input Data Column Mask -- Mask Data Color --
CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS
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-- -- -- 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0
-- -- -- -- -- -- -- 0 1
0 0 0 0 0 0 0 0 0
Stop -- -- Row Row Row Row Row Row Row Row Row (Row) (Row) Mode
Column WM Column WM Column -- Column -- -- -- -- -- WM -- -- Data
Data Sheet E0163H10 7
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0 1 0 0 -- 0 0 0 1 0 0 --
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HM538253B/HM538254B Series
Table 1 Operation Cycles of the HM538253B/HM538254B (cont)
Register Pers W.M. -- Reset -- No Yes No Yes -- -- WM -- Reset -- Load/use Use Load/use Use Color -- -- -- -- -- No. Of Bndry Set Reset -- -- Use -- Use -- -- -- -- Function CBR refresh with stop register set CBR refresh with register reset CBR refresh (no reset) Masked write transfer (new/old mask) Masked split write transfer (new/old mask) Read transfer Split read transfer Read/write (new/old mask) Block write (new/old mask) Read/write (no mask) Block write (no mask) Masked flash write (new/old mask) Load mask register and old mask set Load color resister set
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Mnemonic Code CBRS -- -- -- CBRR CBRN MWT Yes Yes -- -- Yes Yes No No Yes -- -- -- MSWT RT SRT RWM BWM RW (no) BW (no) FWM LMR and Old Mask Set LCR Option 8
Write Mask
Notes: 1. With CBRS, all SAM operations use stop register. 2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR 3. DSF2 is fixed low in all operation (for the addition of operation modes in future).
Operation of HM538253B/HM538254B
RAM Port Operation
RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling edge of CAS: Mnemonic Code; R) Row address is entered at the RAS falling edge and column address at the C AS falling edge to the device as in standard DRAM operation. Then, when WE is high and DT/OE is low while C AS is low, the selected address data outputs through the I/O pin. At the falling edge of RAS , DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and RAS to column address delay time (tRAD ) specifications are added to enable fast page mode/hyper page mode.
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-- -- No Yes No Yes No No Load/use Use Load/use Use -- -- No Yes Set -- -- Load/use Use Load -- --
-- -- --
-- Use
Data Sheet E0163H10
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Use -- -- -- Load -- -- --
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HM538253B/HM538254B Series
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RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write)(DT/OE high, CAS high and DSF1 are low at the falling edge of R AS, and DSF1 is low at the falling edge of CAS): Mnemonic Code; W No Mask Write Cycle (WE high at the falling edge of RAS): When CAS is set low and WE is set low after RAS low, a write cycle is executed. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become in high impedance. If WE is set low after the CAS falling edge, this cycle becomes a delayed write cycle. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If W E is set low after tC W D (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. Mask Write Mode (WE low at the falling edge of RAS):If WE is set low at the falling edge of RAS, two modes of mask write cycle are possible. In new mask mode, mask data is loaded from I/O pin and used. Whether or not an I/O is written depends on I/O level at the falling edge of RAS. The data is written in high level I/Os, and the data is masked and retained in low level I/Os. This mask data is effective during the RAS cycle. So, in page mode cycles the mask data is retained during the page access. If a load mask register cycle (LMR) has been performed, Mask write cycle (RAM write cycle, flash write cycle, block write cycle, masked write transfer cycle and masked sprit write transfer cycle) becomes all persistent mask mode. The mask data is not loaded from I/O pins and the mask data stored in mask registers persistently are used. This operation known as persistent write mask is reset by CBRR cycle, and becomes a new mask. Fast Page Mode Cycle (HM538253B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS): Fast page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Hyper Page Mode Cycle (HM538254B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS): Hyper page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one forth of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (t AA ), RAS to column address delay time (tRAD), and access time from CAS precharge (t ACP ) are added. column address is latched by CAS low edge triger, access time from CAS is determined by tCAC (tAA from column address, t ACP from CAS high edge). Dout data is held during CAS high and is sustained until next Dout. Data output enable/disable is controlled by DT/OE and when both RAS and CAS become high, Data output becomes High-Z. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Color Register Set/Read Cycle (CAS high, DT/OE high, W E high and DSF1 high at the falling edge of RAS: Mnemonic Code; LCR) In color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 8 bits of internal color register are provided at each I/O. This register is composed of static circuits, so once it is set, it retains the data until reset. Since color register set cycle is the
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Data Sheet E0163H10 9
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HM538253B/HM538254B Series
same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS. Mask Register Set/Read Cycle (CAS high, DT/OE high, WE high, and DSF1 low at the falling edge of R AS: Mnemonic Code; LMR) In this cycle, mask data is set to the internal mask register persistently used in mask write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 8 bits of internal mask register are provided at each I/O. This mask register is composed of static circuits. So once it is reset by CBRR cycle, it retains the data until reset or reselect. Once LMR is set, mask write cycle data is written by persistent mask data. Since mask register set cycle is just the same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. Flash Write Cycle (CAS high, D T/OE high, W E low, and DSF1 high at the falling edge of R A S: Mnemonic; FW) In a flash write cycle, a row of data (512 word x 8 bit) is cleared to 0 or 1 at each I/O according to the data in the color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE are set high, WE is low, and DSF1 is high at the falling edge of RAS, this cycle starts. Then, the row address to clear is given to row address. Mask data is the same as that of a RAM write cycle. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.) Block Write Cycle (CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WE low at the falling edge of CAS: Mnemonic; BW) In a block write cycle, 4 columns of data (4 column x 8 bit) are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The mask data on I/Os and the mask data on column address can be determined independently. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) The block write cycle is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write cycle can be executed. No Mask Mode Block Write Cycle (WE high at the falling edge of RAS): The data on 8 I/Os are all cleared when WE is high at the falling edge of RAS. Mask Block Write Cycle (WE low at the falling edge of RAS):When WE is low at the falling edge of RAS, the HM538253B/HM538254B starts mask block write cycle to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O does not care about mask mode.
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Data Sheet E0163H10
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HM538253B/HM538254B Series
Flash Write Cycle Flash Write Cycle
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RAS CAS Address WE Row DT/OE DSF1 I/O
Color Register Set Cycle
Xi
Xj
Set color register
Note: 1. I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care
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Color Data
*1
*1 Execute flash write into each I/O on row address Xi using color register. Execute flash write into each I/O on row address Xj using color register.
Figure 1 Use of Flash Write
Data Sheet E0163H10 11
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HM538253B/HM538254B Series
Color Register Set Cycle Block Write Cycle Block Write Cycle
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RAS CAS Address WE DT/OE DSF1 I/O *1 12
Row
Row *1
Column A2-A8
Row *1
Column A2-A8
WE Low
High
I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O H or L Column Mask Data I/O0 I/O1 I/O2 I/O3
Transfer Operation
The HM538253B/HM538254B provides the read transfer cycle, split read transfer cycle, masked write transfer cycle and masked split write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: * Transfer data between row address and SAM data register Read transfer cycle and split read transfer cycle: RAM to SAM Masked write transfer cycle and masked split write transfer cycle: SAM to RAM * Determine SI/O state (except for split read transfer and masked split write transfer cycle) Read transfer cycle: SI/O output Masked write transfer cycle: SI/O input * Determine first SAM address to access after transferring at column address (SAM start address).
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Color Data Mode New mask mode Persistent mask mode No mask
*1
Column Mask
*1
Column Mask
I/O data/RAS Mask H or L (mask register used) H or L
Column0 (A0 = 0, A1 = 0) Mask Data Column1 (A0 = 1, A1 = 0) Mask Data Column2 (A0 = 0, A1 = 1) Mask Data Column3 (A0 = 1, A1 = 1) Mask Data
Figure 2 Use of Block Write
Data Sheet E0163H10
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Low: Mask High: Non Mask
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HM538253B/HM538254B Series
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RAS CAS Address DT/OE DSF1 SC SI/O
SAM start address must be determined by read transfer cycle or masked write transfer cycle (split transfer cycle isn't available) before SAM access, after power on, and determined for each transfer cycle. * Use the stopping columns (boundaries) in the serial shift register. If the stopping columns have been set, split transfer cycles use the stopping columns, but any boundaries cannot be set as the start address. * Load/use mask data in masked write transfer cycle and masked split write transfer cycle. Read Transfer Cycle (CAS high, D T/OE low, W E high and DSF1 low at the falling edge of R A S): Mnemonic; RT This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF1 low at the falling edge of RAS. The row address data (512 x 8 bits) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must rise to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.)
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. Masked Write Transfer cycle (CAS high, DT/OE low, WE low, and DSF1 low at the falling edge of RAS): Masked write transfer cycle can transfer only selected I/O data in a row of data input by serial write cycle to RAM. Whether I/O data is transferred or not depends on the corresponding I/O level (mask data) at the falling
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Xi L
SAM Data before Transfer
Figure 3 Real Time Read Transfer
Data Sheet E0163H10 13
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Yj t SDD
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t SDH
Yj
Yj + 1
SAM Data after Transfer
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HM538253B/HM538254B Series
edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the persistent mode can be supported. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8). Figure 4 shows the example of row bit data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111. Same as the case of AX8 = 1.
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(Row address) A8 ........ A0 000000000 011111111 100000000 111111111 14
(Read transfer cycle)
Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF1 high at the falling edge of RAS): To execute a continuous serial read by real-time read transfer, the HM538253B/HM538254B must satisfy SC and DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. The HM538253B/HM538254B supports two types of split register operation. One is the normal split register operation to split the data register into two halves. The other is the boundary split register operation using stopping columns described later. Figure 5 shows the block diagram for the normal split register operation. SAMdata register (DR) consists of 2 split buffers, whose organizations are 256-word x 8-bit each. Suppose that data is read from upper data register DR1. (The row address AX8 is 0 and SAM address A8 is 1.) When split read transfer is executed setting row address AX8 to 0 and SAM start addresses A0 to A7, 256-word x 8-bit data is transferred from RAM to the lower data register DR0 (SAM address A8 is 0) automatically. After data is read from data register DR1, data read begins from SAM start addresses of data register DR0. If the next split read transfer isn't executed while data is read from data register DR0, data read begins from SAM start address 0 of DR1 after data is read from data register DR0. If split read transfer is executed setting row address AX8 to 1 and SAM start addresses A0 to A7 while data is read from data register DR1, 256-word x 8-bit data is transferred to data register DR2. After data is read from data register DR1, data read begins from the SAM start addresses
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SAM ........ RAM RAM SAM
(Row address) A8 ........A0 000000000 011111111 100000000 111111111
SAM Possible RAM Impossible RAM SAM (Write transfer cycle)
Figure 4 Example of Row Bit Data Transfer
Data Sheet E0163H10
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HM538253B/HM538254B Series
SAM Column Decoder
DR1
SAM I/O Bus
AX8 = 0
SAM I/O Bus
Memory Array
DR3
DR0
SAM I/O Buffer
SI/O
Figure 5 Split Transfer Block Diagram Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF1 is high at the falling edge of RAS. The cycle can be executed asyncronously with SC. However, the HM538253B/ HM538254B must be satisfied tSTS (min) timing specified between SC rising (boundary address) and RAS falling. In split transfer cycle, the HM538253B/HM538254B must satisfy t RST (min), tCST (min) and tAST (min) timings specified between RAS or CAS falling and column address. (See figure 6.) In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch SI/O to output state when the previous transfer cycle is masked write transfer cycle or masked split write transfer cycle. Masked Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF1 high at the falling edge of RAS): A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write transfer. Masked split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state in this cycle. If SI/O is in output state, masked write transfer cycle should be executed to switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by masked split write transfer cycle. However masked write transfer cycle must be executed before masked split write transfer cycle. And in this masked split write transfer cycle, the
DR2
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of data register DR2. If the next split read transfer isn't executed while data is read from data register DR2, data read begins from SAM start address 0 of data register DR1 after data is read from data register DR2. In split read data transfer, the SAM start address A8 is automatically set in the data register, which isn't used. The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to high by accessing SAM last address 255 and from high to low by accessing address 511.
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Memory Array AX8 = 1
Data Sheet E0163H10 15
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HM538253B/HM538254B Series
MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. In this cycle, the boundary split register operation using stopping columns is possible as with split read transfer cycle.
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RAS CAS Address DT/OE DSF1 SC
tSTS (min)
tRST (min)
Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address.
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Xi Bi A2 0 1 1 1 1 1 1 4 8 16 32 64 128 256
t CST (min) Yj
t AST (min)
Ym
Bj - 1
Bj
Yj
Figure 6 Split Transfer Limitation Table 2 Stopping Column Boundary Table
Stop Address Boundary Code Column Size B2 B3 B4 B5 B6 B7 B8 A3 x 0 1 1 1 1 1
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x x 0 1 1 1 1
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A4 A5 x x x x x x 0 1 x 0 1 1 1 1
A6
A7 x x x x x 0 1
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Notes: 1. A0, A1, and A8: H or L 2. x: H or L
Stopping Column in Split Transfer Cycle: The HM538253B/HM538254B has the boundary split register operation using stopping columns. If a CBRS cycle has been performed, split transfer cycle performs the boundary operation. Figure 7 shows an example of boundary split register. (Boundary code is B7.)
Data Sheet E0163H10 16
HM538253B/HM538254B Series
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First a read data transfer cycle is executed, and SAM start addresses A0 to A8 are set. The RAM data is transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After that, a split read transfer cycle is executed, and the next start address (Y2) is set. The RAM data is transferred to the upper SAM. When the serial read arrive at the first boundary after the split read transfer cycle, the next read jumps to the start address (Y2) on the upper SAM (jump 1) and continues. Then the second split read transfer cycle is executed, and another start address (Y3) is set. The RAM data is transferred to the lower SAM. When the serial read arrive at the other boundary again, the next read jumps to the start address (Y3) on the lower SAM. In stopping column, split transfer is needed for jump operation between lower SAM and upper SAM.
Stopping Column Set Cycle (CBRS): Start a stopping column set cycle by driving CAS low, WE low, and DSF1 high at the falling edge of R AS. Stopping column data (boundaries) are latched from address inputs on the falling edge of RAS. To determine the boundary, A2 to A7 can be used, and A0, A1, and A8 don't care. In the HM538253B/HM538254B, 7 types of boundary (B2 to B8) can be set including the default case. (See stopping column boundary table.) If A2 to A6 are set high and A7 is set low, the boundaries (B7) are selected. Figure 6 shows the example. Once a CBRS is executed, next sprit transfer cycle data become stopping columm data. Stopping columm is reset by CBBR.
Column size 128 bit
Register Reset Cycle (CBRR): Start a register reset cycle (CBRR) by driving CAS low, W E high, and DSF1 low at the falling edge of R AS. A CBRR can reset the persistent mask operation and stopping column operation, so the HM538253B/HM538254B becomes the new mask operation and boundary code B8. When a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy t STS (min) and tRST (min) between RAS falling and SC rising. No Reset CBR cycle (CBRN): This cycle becomes no reset CBR cycle (CBRN) by driving CAS low, WE high and DSF1 high at the falling edge of RAS. The CBRN can only execute the refresh operation.
LP
(Y1) Start Jump 1
Boundaries (B7)
Lower SAM 256 bit
Figure 7 Example of Boundary Split Register
Data Sheet E0163H10 17
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(Y3)
(Y2)
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Upper SAM 256 bit
Jump 2
ct
HM538253B/HM538254B Series
SAM Port Operation
Serial Read Cycle
EO
Serial Write Cycle
SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access.
If the previous data transfer cycle is a masked write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into the data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into the data register. The internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access.
LP
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh cycles to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2) CAS-before-R AS (CBRN, CBRS, and CBRR) refresh cycle, and (3) Hidden refresh cycle. The cycles which activate RAS, such as read/write cycles or transfer cycles, can also refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. RAS-Only Refresh Cycle: R AS-only refresh cycle is executed by activating only the RAS cycle with C AS fixed high after inputting the row address (refresh address) from external circuits. To distinguish this cycle from a data transfer cycle, DT/OE must be high at the falling edge of RAS. CBR Refresh Cycle: CBR refresh cycle (CBRN, CBRS and CBRR) is set by activating CAS before RAS. In this cycle, the refresh address needs not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is high impedance and power dissipation is low because CAS circuits are not operating. Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles.
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du
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SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
Data Sheet E0163H10 18
HM538253B/HM538254B Series
EO
Parameter Power dissipation Storage temperature Parameter Supply voltage Input high voltage Input low voltage
Absolute Maximum Ratings
Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -0.5 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current
Operating temperature
Recommended DC Operating Conditions (Ta = 0 to +70C)
Symbol VCC Min Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Notes 1 1 1 4.5 2.4
Notes: 1. All voltage referred to VSS 2 -3.0 V for pulse width 10 ns.
LP
VIH VIL -0.5
*2
Data Sheet E0163H10 19
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HM538253B/HM538254B Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM538253B/HM538254B -7 -8 -10 Max Unit Test Conditions 90 mA RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS = VIH SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling CAS = VIH t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min
EO
Parameter Operating current Block write current Standby current RAS-only refresh current Fast page mode current (HM538253B) *3 20
Symbol Min Max Min Max Min I CC1 -- 110 -- 100 --
I CC7
--
165 --
150 --
140 mA
Fast page mode I CC4BW block write current *3 I CC10BW
LP
I CC1BW -- 115 -- I CC7BW -- 170 -- I CC2 -- -- 7 -- I CC8 65 -- I CC3 -- 110 -- I CC9 -- 165 -- I CC4 -- 110 -- I CC10 -- 160 -- -- 130 -- -- 185 --
105 --
90
mA
155 --
140 mA
7 60
-- --
7 55
mA mA
Data Sheet E0163H10
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100 -- 150 -- 105 -- 155 -- 125 -- 175 --
90
mA
135 mA
100 mA
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150 mA 120 mA 165 mA
CAS cycling RAS = VIL t PC = min
ct
HM538253B/HM538254B Series
EO
Parameter Hyper page mode current (HM538254B) *3 CAS-before-RAS refresh current Input leakage current Output leakage current Output low voltage
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont)
HM538253B/HM538254B -7 -8 -10 Max Unit Test Conditions 110 mA CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min CAS cycling RAS = VIL t PC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min RAS, CAS cycling t RC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min
Symbol Min Max Min Max Min I CC4 -- 130 -- 120 --
I CC10
--
185 --
170 --
160 mA
Hyper page mode I CC4BW block write current *3
Data transfer current I CC6
Output high voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. 3. Address can be changed once in 1 page cycle (tPC).
LP
-- 155 -- I CC10BW -- 210 -- I CC5 -- -- 85 -- I CC11 140 -- -- 130 -- I CC12 -- 180 -- I LI I LO -10 10 -10 10 2.4 -- -- 0.4 2.4 --
140 --
130 mA mA 175 175
190 --
75
--
65
mA
130 --
120 mA
-10 10 -10 10 -- 0.4
Data Sheet E0163H10 21
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115 -- 165 -- -10 -10 2.4 --
100 mA
145 mA
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10 10 A A -- V V 0.4
I OH = -1 mA I OL = 2.1 mA
ct
HM538253B/HM538254B Series
Capacitance (Ta = 25C, VCC = 5 V 10%, f = 1 MHz, Bias: Clock, I/O = VCC, Address = VSS)
Parameter Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 5 7 Unit pF pF pF Note 1 1 1 Input capacitance (Address) Input capacitance (Clocks) Output capacitance (I/O, SI/O, QSF) Note:
EO
Test Conditions * * * * *
22
1. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *16
Input rise and fall time: 5 ns Input pulse levels: VSS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: RAM 1 TTL + CL (50 pF) SAM, QSF 1 TTL + CL (30 pF) (Including scope and jig)
LP
Data Sheet E0163H10
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HM538253B/HM538254B Series
EO
Parameter RAS precharge time RAS pulse width CAS pulse width Refresh period DT to RAS hold time
Common Parameter
HM538253B/HM538254B -7 Symbol Min Max t RC t RP t RAS t CAS 130 -- 50 70 20 0 10 0 12 20 20 70 10 3 -- 10000 -- -- -- -- -- 50 -- -- -- 50 8 -8 Min Max 150 -- 60 80 20 0 10 0 15 20 20 80 10 3 -- 0 10 0 10 0 -- 10000 -- -- -- -- -- 60 -- -- -- 50 8 -- -- -- -- -- -10 Min Max 180 -- 70 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns 4 4 5 5 3 2
Random read or write cycle time
100 10000 25 0 10 0 15 20 25 -- -- -- -- -- 75 --
Row address setup time Row address hold time
Column address setup time Column address hold time RAS to CAS delay time
RAS hold time referred to CAS CAS hold time referred to RAS CAS to RAS precharge time Transition time (rise to fall)
DT to RAS setup time DSF1 to RAS setup time DSF1 to RAS hold time DSF1 to CAS setup time DSF1 to CAS hold time Data-in to CAS delay time Data-in to OE delay time Output buffer turn-off delay referred to CAS Output buffer turn-off delay referred to OE
LP
t ASR t RAH t ASC t CAH t RCD t RSH t CSH t CRP tT t REF t DTS t DTH t FSR t RFH t FSC t CFH t DZC t DZO t OFF1 t OFF2
100 -- 10 3 -- 0 10 0 10 0 15 -- 50 8 -- -- -- -- -- -- -- -- 20 20
Data Sheet E0163H10 23
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-- 0 -- 10 0 -- -- 10 0 -- -- 12 0 0 -- -- -- -- -- 15 15
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15 -- 0 0 -- -- -- -- 20 20
0 0 -- --
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HM538253B/HM538254B Series
Read Cycle (RAM), Page Mode Read Cycle
HM538253B/HM538254B -7 Symbol Min Max t RAC t CAC t OAC t AA -- -- -- -- 0 0 0 15 35 35 45 7 -- 70 20 20 35 -- -- -- 35 -- -- -- -- 40 -8 Min Max -- -- -- -- 0 0 5 15 40 40 50 10 -- 80 20 20 40 -- -- -- 40 -- -- -- -- 45 -10 Min Max -- -- -- -- 0 0 10 15 45 45 55 10 -- 100 25 25 45 -- -- -- 55 -- -- -- -- 50 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 2 6, 7 7, 8 7 7, 9
EO
Parameter Access time from OE Address access time CAS precharge time 24
Access time from RAS Access time from CAS
Read command setup time Read command hold time
Read command hold time referred to RAS RAS to column address delay time Column address to RAS lead time Column address to CAS lead time Page mode cycle time
Access time from CAS precharge Page mode RAS pulse width
LP
t RCS t RCH t RRH t RAD t RAL t CAL t PC t CP t ACP t RASP
Data Sheet E0163H10
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70
100000 80
100000 100 100000 ns
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HM538253B/HM538254B Series
EO
Parameter Data-in setup time Data-in hold time WE to RAS hold time CAS precharge time
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM538253B/HM538254B -7 Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS 0 12 12 20 20 0 12 0 10 0 10 15 45 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 50 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 55 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 12 12 11
Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time
WE to RAS setup time
Mask data to RAS setup time Mask data to RAS hold time OE hold time referred to WE Page mode cycle time
CAS to data-in delay time Page mode RAS pulse width
LP
t DH t WS t WH t MS t MH t OEH t PC t CP t CDD t RASP
Data Sheet E0163H10 25
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15 70
100000 80
100000 100 100000 ns
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HM538253B/HM538254B Series
Read-Modify-Write Cycle
HM538253B/HM538254B -7 Symbol Min Max t RWC t RWS t CWD t AWD 180 -- 120 10000 40 60 15 -- -- -- -- 15 0 20 20 12 0 -- -- -- 70 20 20 35 35 -- -- -- -- -8 Min Max 200 -- 130 10000 45 65 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 80 20 20 40 40 -- -- -- -- -- -- -- -10 Min Max 230 -- 150 10000 50 70 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 100 25 25 45 55 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 14 14 12 6, 7 7, 8 7 7, 9
EO
Parameter Access time from OE Address access time Data-in setup time Data-in hold time
Read-modify-write cycle time RAS pulse width (read-modify-write cycle) CAS to WE delay time
Column address to WE delay time OE to data-in delay time Access time from RAS Access time from CAS
RAS to column address delay time Read command setup time Write command to RAS lead time Write command to CAS lead time Write command pulse width
OE hold time referred to WE
LP
t ODD t RAC t CAC t OAC t AA t RAD t RCS t RWL t CWL t WP t DS t DH t OEH t CSR t CHR t RPC
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-- 12 15 -- -- -7 10 10 10 -- -- --
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-8 Min Max -- -- -- 10 10 10
Refresh Cycle
HM538253B/HM538254B
-10 Min Max -- -- -- Unit Notes ns ns ns
Parameter CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS precharge to CAS hold time
Symbol Min Max
10 10 10
ct
Data Sheet E0163H10 26
HM538253B/HM538254B Series
EO
Parameter Parameter Parameter
Flash Write Cycle, Block Write Cycle, and Register Read Cycle
HM538253B/HM538254B -7 Symbol Min Max t CDD t ODD 15 15 -- -- -8 Min Max 20 20 -- -- -10 Min Max 20 20 -- -- Unit Notes ns ns 13 13
CAS to data-in delay time OE to data-in delay time
CBR Refresh with Register Reset
Split transfer setup time
Split transfer hold time referred to RAS
Hyper Page Mode Cycle (HM538254B)
Column address to CAS lead time Hyper page mode cycle time Hyper page CAS precharge time Hyper page data out hold time Data-out buffer turn-off time (RAS) Data-out buffer turn-off time (CAS) RAS to data-in delay time
LP
t STS t RST t CAL t PC t CP t DOH t RHZ t CHZ t RDD
HM538253B/HM538254B -7 -8 Min Max 20 80 -- -- -10 Min Max 25 -- Unit Notes ns ns
Symbol Min Max 20 70 -- --
100 --
Symbol Min Max 25 35 5 4 -- -- 20 -- -- --
Data Sheet E0163H10 27
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-7 -- 15 15 --
HM538254B -8 Min Max 30 40 10 -- -- -- -10 Min Max 35 45 10 -- -- -- -- 20 20 -- Unit Notes ns ns ns ns ns ns ns 5 5 13
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5 -- -- -- 20 20 -- 20
5 -- -- 20
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HM538253B/HM538254B Series
Read Transfer Cycle
HM538253B/HM538254B -7 Symbol Min Max t RDH t CDH t ADH t DTP 60 20 25 20 60 15 70 25 40 5 10 -- 5 0 10000 -- -- -- -- -- -- -- -- -- -- 30 -- -- -8 Min Max 65 20 30 20 70 20 80 25 45 5 13 -- 5 0 28 10 10 -- 5 0 10000 -- -- -- -- -- -- -- -- -- -- 35 -- -- -- -- -- 23 -- -- -10 Min Max 80 25 30 30 80 30 10000 -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15 15
EO
Parameter DT precharge time SC pulse width SC precharge time SC access time 28
DT hold time referred to RAS DT hold time referred to CAS DT hold time referred to DT to RAS delay time
SC to RAS setup time
1st SC to RAS hold time 1st SC to CAS hold time
1st SC to column address hold time Last SC to DT delay time 1st SC to DT hold time DT to QSF delay time
QSF hold time referred to DT
Serial data-in to 1st SC delay time Serial clock cycle time
Serial data-out hold time Serial data-in setup time Serial data-in hold time RAS to column address delay time Column address to RAS lead time RAS to QSF delay time CAS to QSF delay time QSF hold time referred to RAS QSF hold time referred to CAS
LP
t DRD t SRS t SRH t SCH t SAH t SDD t SDH t DQD t DQH t SZS t SCC t SC t SCP t SCA t SOH t SIS t SIH t RAD t RAL t RQD t CQD t RQH t CQH
100 -- 25 50 5 15 -- 5 0 30 10 10 -- 5 0 15 15 -- -- -- -- 35 -- -- -- -- -- 25 -- -- -- 55 -- 85 35 -- --
Data Sheet E0163H10
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25 5 -- -- -- 10 -- 5 0 15 15 35 -- -- 20 5 20 -- -- -- 35 -- 70 35 -- --
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15 -- 15 40 40 -- -- -- 75 35 -- 20 5 --
45
-- -- 25
5
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HM538253B/HM538254B Series
EO
Parameter SC pulse width SC precharge time SC access time
Masked Write Transfer Cycle
HM538253B/HM538254B -7 Symbol Min Max t SRS t SRD t SRZ t SID 15 20 10 30 -- -- 20 5 25 5 10 -- 5 0 -- -- 30 -- 70 35 -- -- -- -- -- 20 -- -- -8 Min Max 20 25 10 35 -- -- 20 5 28 10 10 -- 5 0 15 -- -- 35 -- 75 35 -- -- -- -- -- 23 -- -- -- -10 Min Max 30 25 10 50 -- -- 25 5 30 10 10 -- 5 0 15 -- -- 50 -- 85 35 -- -- -- -- -- 25 -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 15
SC setup time referred to RAS RAS to SC delay time Serial output buffer turn-off time referenced to RAS RAS to serial data-in delay time RAS to QSF delay time CAS to QSF delay time
QSF hold time referred to RAS
QSF hold time referred to CAS Serial clock cycle time
Serial data-out hold time Serial data-in setup time Serial data-in hold time
LP
t RQD t CQD t RQH t CQH t SCC t SC t SCP t SCA t SOH t SIS t SIH
Data Sheet E0163H10 29
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15 --
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HM538253B/HM538254B Series
Split Read Transfer Cycle, Masked Split Write Transfer Cycle
HM538253B/HM538254B -7 Symbol Min Max t STS t RST t CST t AST 20 70 20 35 -- 5 25 5 10 -- 5 0 15 15 35 -- -- -- -- 30 -- -- -- -- 20 -- -- -- -8 Min Max 20 80 20 40 -- 5 28 10 10 -- 5 0 15 15 40 -- -- -- -- 30 -- -- -- -- 23 -- -- -- 40 -- -10 Min Max 25 -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15
EO
Parameter SC pulse width SC precharge time SC access time Parameter SC pulse width SC precharge width Access time from SC Access time from SE 30
Split transfer setup time Split transfer hold time referred to RAS Split transfer hold time referred to CAS Split transfer hold time referred to column address SC to QSF delay time
100 -- 25 45 -- 5 30 10 10 -- 5 0 15 15 45 -- -- 30 -- -- -- -- 25 -- -- -- 55 --
QSF hold time referred to SC Serial clock cycle time
Serial data-out hold time Serial data-in setup time Serial data-in hold time
RAS to column address delay time Column address to RAS lead time
Serial Read Cycle, Serial Write Cycle
Serial clock cycle time
Serial data-out hold time
Serial output buffer turn-off time referred t SHZ to SE SE to serial output in low-Z Serial data-in setup time t SLZ t SIS
LP
t SQD t SQH t SCC t SC t SCP t SCA t SOH t SIS t SIH t RAD t RAL t SCC t SC t SCP t SCA t SEA t SOH
Symbol Min Max 25 5 10 -- -- 5 -- 0 0 -- -- -- 20 17 -- 15 -- --
Data Sheet E0163H10
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35 -- -7
HM538253B/HM538254B -8
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Min Max -- -- -- 28 10 10 -- -- 5 -- 0 0 23 20 -- 20 -- --
-10 Min Max -- -- -- 25 25 -- Unit Notes ns ns ns ns ns ns 15 15
30 10 10
-- -- 5
ct
-- 0 20 -- ns ns 0 -- ns
5,17 5,17
HM538253B/HM538254B Series
EO
Parameter
Serial Read Cycle, Serial Write Cycle (cont)
HM538253B/HM538254B -7 Symbol Min Max t SIH t SWS t SWH t SWIS 15 0 15 0 15 -- -- -- -- -- -8 Min Max 15 0 15 0 15 -- -- -- -- -- -10 Min Max 15 0 15 0 15 -- -- -- -- -- Unit Notes ns ns ns ns ns
Serial data-in hold time Serial write enable setup time Serial wrtie enable hold time Serial write disable setup time Serial write disable hold time
Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. t RHZ (max), tCHZ (max), tOFF1 (max), tOFF2 (max), tSHZ (max) and tSLZ (min) are defined as the time at which the output acheives the open circuit condition (VOH - 100 mV, VOL + 100 mV). This parameter is sampled and not 100% tested. 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 8. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC . 9. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA . 10. If either tRCH or tRRH is satisfied, operation is guaranteed. (HM538253) If both tRCH and t RRH are satisfied, operation is guaranteed, (HM538254) 11. When t WCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WE. 13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. (HM538253B) Either t CDD (min), tODD (min) or tRDD (min) must be satisfied because the output buffer must be turned off by CAS, OE or RAS prior to applying data to the device when output buffer is on. (HM538254B) 14. When t AWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 1 TTL loads and 30 pF. 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. Hitachi recommends that least 8 initialization cycle is CBRR for internal register reset. 17. When t SHZ and t SLZ are measured in the same V CC and Ta condition and tr and tf of SE are less than 5 ns, t SHZ < tSLZ + 5 ns. 18. After power-up, QSF output may be High-Z, so 1SC cycle is needed to be Low-Z it. 19. DSF 2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition mode in future.
LP
t SWIH
Data Sheet E0163H10 31
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HM538253B/HM538254B Series
20. XXX: H or L (H : VIH (min) V IN V IH (max), L : VIL (min) V IN V IL (max) ///////: Invalid Dout
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Timing Waveforms*20
Read Cycle (HM538253B)
t RC t RAS t CSH t RSH t CAS t RAL t CAH t RRH t CAC t AA t RAC t OAC t OFF1 Valid Dout t OFF2 t CAL t RP t CRP
LP
t RCD t ASR t RAD t RAH t ASC Row t DZC t DZO t DTS t FSR t DTH t RFH t FSC
Column t RCS
t RCH t CDD
Data Sheet E0163H10 32
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t CFH
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HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Fast Page Mode Read Cycle (HM538253B)
t RC t RASP t CSH t CAS t RCD t RAD t ASR t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH Column t RCS t RCH t AA t ACP t CAC t DZC t OAC t OFF1
Valid Dout
t RP t RSH t CAS
t CP t RAL t ASC
t CRP
t ASC
t CAL t CAH Column t RCS t AA t ACP t CAC
Valid Dout
LP
Column t RCS t RCH
Valid Dout
t RRH t RCH
t RAC t OFF1 t AA t CAC t CDD t OAC t OFF2
t OFF1
t DZC
t CDD t OFF2
t DZC t OAC
t CDD
t DTS
t DZO t DTH t RFH
t FSR
t FSC
t CFH
t FSC
t CFH
t FSC
t CFH
Data Sheet E0163H10 33
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HM538253B/HM538254B Series
Write Cycle
EO
Table 3
Menu RWM BWM RW BW LMR*4 LCR*4 Cycle Notes: 1. WE Low High 34
Table 3 below applies to early write, delayed write, page mode write, and read-modify write. Write Cycle State
RAS DSF1 W1 0 0 CAS DSF1 W2 0 1 0 1 0 1 RAS WE W3 0 0 1 1 1 1 RAS I/O W4 Write mask
*1
CAS I/O W5 Valid data Column mask*2 Valid data Column mask*2 Write mask data*3 Color data
Write mask (new/old) Write DQs to I/Os Write mask (new/old) Block write
Normal write (no mask) Block write (no mask)
Load write mask resister Load color resister Mode
New mask mode
Persistent mask mode No mask
I/O Mask data (In new mask mode) Low: Mask High: Non mask In persistent mask mode, I/O H or L 2. Reference Figure 2 use of block write. 3. I/O write mask data Low: Mask High: Non mask 4. Column Address: H or L
LP
0 0 1 1
Write mask*2 Don't care*1 Don't care
*2
Don't care Don't care
I/O data/RAS
Mask
H or L (mask register used) H or L
Data Sheet E0163H10
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HM538253B/HM538254B Series
EO
Early Write Cycle
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
t RC t RAS t CSH t RCD t ASR Row W3 t RAH t ASC Column t WCH t RSH t CAS t CAH t RP t CRP
WI to W5: See write cycle state table for the logic states.
LP
t WS t WH t WCS t MS t MH t DS W4 W5 t DTS t DTH t FSR t RFH t FSC W1 W2
High-Z
t DH
t CFH
Data Sheet E0163H10 35
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HM538253B/HM538254B Series
Delayed Write Cycle
t RC t RAS t CSH t RSH t CAS t ASR t RAH t ASC Column t RWL t WP t CWL t CAH t RP t CRP
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
t RCD
Row
WI to W5: See write cycle state table for the logic states.
Fast/Hyper Page Mode Write Cycle (Early Write)
t DTS t FSR
WI to W5: See write cycle state table for the logic states.
LP
t WS t WH W3 t MS t MH t DZC W4 t DTS t DTH t FSR t RFH t FSC W1 W2 t CSH t RCD t ASR t RAH t ASC t CAS Row Column t WS t WH t WCS t WCH W3 t MS t MH W4 t DTH t RFH t FSC W1 W2 t CFH t DS t DH W5
t DS
t DH W5 t OEH
t OFF2 t ODD t CFH
t CAH t ASC Column
Data Sheet E0163H10 36
ro
t RC t RASP t PC t CP t CAS t WCS t WCH t DS t DH W5 t FSC W2 t CFH
t RP
t CAH t ASC
High-Z
du
t CP t RSH t CAS t CAH Column t WCS t WCH t DS t DH W5 t FSC W2 t CFH
t CRP
ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 t DTS t FSR RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Fast/Hyper Page Mode Write Cycle (Delayed Write)
t RC t RASP
t RP
t CSH t RCD t CAS t CAH t CWL t CP t ASC
t PC t CAS t CAH t CWL t WP
t CP
t RSH t CAS t CAH t RWL t WP
t CRP
t ASR t RAH t ASC Row Column
t ASC Column
Column
t WS
t MS
WI to W5: See write cycle state table for the logic states.
Read-Modify-Write Cycle
WI to W5: See write cycle state table for the logic states.
LP
t WH t WP W3 t MH t DS t DH W5 W4 t RFH t FSC t CFH W1 W2 t RCD t RAD t ASR t RAH t ASC Row t WS t WH W3 tRCS t MS t MH t DZC t DZO W4 t DTS t DTH t FSR W1 t RFH t FSC W2
t CWL
High-Z t DS t DH W5 t DS t DH W5 t OEH t FSC t CFH W2 t FSC t CFH
W2
Column
Data Sheet E0163H10 37
ro
t RWC t RWS t CAH t AWD t CWD t CAC t AA t RAC t OAC t CFH
t RP t CRP
du
Valid Dout t DS t DH t OFF2 t ODD W5
t RWL t CWL t WP
t OEH
ct
HM538253B/HM538254B Series
RAS-Only Refresh Cycle (HM538253B)
t RC t RAS t CRP t ASR t RAH t RPC t RP
EO
RAS CAS Address I/O (Output) I/O (Input) DT/OE DSF1 RAS CAS Address WE I/O (Output) DT/OE DSF1
Row
t OFF1
CAS-Before-RAS Refresh Cycle (CBRN) (HM538253B)
LP
t CDD t OFF2 t ODD t DTS t DTH t FSR t RFH t RP t RPC t CP t CSR t WS t OFF1 t FSR
WE : H or L
Data Sheet E0163H10 38
ro
t CHR t WH High-Z t RFH
t RC t RAS t RP t CSR
t RPC Inhibit Falling Transition
du ct
SC : H or L
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Hidden Refresh Cycle (HM538253B)
t RC t RAS t RCD t RP t RSH t RAS t RC t RP t CRP
t CHR
t ASR Row
t RAD t RAL t RAH t ASC t CAH Column t RCS t WH
CAS-Before-RAS Set Cycle (CBRS)
LP
t CAC t AA t RAC t DZC t DTS t DZO t DTH t FSR t RFH t FSC t CFH
t RRH
t WS
t OFF1 Valid Dout t OFF2
t OAC
t FSR
t RFH
ro
t CHR t RAH t RFH
t RC t RP
t RP RAS t RPC CAS t ASR *1 Address (A2-A7) WE I/O (Output) I/O (Input) DT/OE t FSR DSF1 Note: A0, A1, A8: H or L SC: H or L t CSR
t RAS
t CRP
du
High-Z
Inhibit falling transition
Stop Address t WS t WH
ct
39
Data Sheet E0163H10
HM538253B/HM538254B Series
CAS-Before-RAS Reset Cycle (CBRR)
t RC t RP t RAS t RP
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 SC 40
t RPC
t CSR
t CHR
Inhibit falling transition
t CRP
Notes: 1. Bi, Bj initiate the boundary addresses. When a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy tSTS (min) and tRST (min) between RAS falling and SC rising. 2. Ym, Yn are the SAM start address in before SRT/MSWT.
LP
t WS t FSR t STS Bi*1
t WH High-Z
t RFH t RST
Data Sheet E0163H10
ro
Bj-2
Bj-1
Bj*1
du ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Flash Write Cycle (HM538253B)
t RC t RAS t CRP t ASR Row t WS t WH t RCD t RAH t RP
t OFF1 t OFF2
LP
t CDD t ODD t MS t DTS t FSR
High-Z
t MH
Mask Data t DTH t RFH
Data Sheet E0163H10 41
ro du ct
HM538253B/HM538254B Series
Register Read Cycle (Mask data, Color data) (HM538253B)
t RC t RAS t CSH t CAS t RP t CRP t RSH
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 42
t RCD t ASR t RAH
Note: 1. State of DFS1 at falling edge of CAS State Accessed data 0
LP
Row t WS t WH t RCS t RAC t DZC t DTS t FSR t DZO t DTH t RFH t FSC
*1
t RRH t CAC t OFF1 t OAC Valid Out t OFF2 t ODD
t RCH
t CDD
Mask data (LMR)
Data Sheet E0163H10
ro
t CFH 1 Color data (LCR)
du ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input) QSF
Read Transfer Cycle 1
tRC t RAS t CSH t RCD t RSH t CAS t RAL t ASC t CAH
SAM Start Address
t RP t CRP
t ASR Row
t RAD t RAH
Valid Sout
LP
t WS t WH t DTS t FSR t RFH t SCC t SCA t SOH t SCA t SOH Valid Sout SAM Address MSB
High-Z t CDH t ADH t RDH t DTP t DRD
t SCC t SDD t SCA t SOH
t SCC t SDH
t SCC t SC t SCA t SOH t SCP t SOH Valid Sout New Row
Data Sheet E0163H10 43
ro
Valid Sout High-Z
Valid Sout
Previous Row t DQD
t DQH
du ct
HM538253B/HM538254B Series
Read Transfer Cycle 2
t RC t RAS t RP
EO
RAS CAS Address WE I/O (Output) DT/OE
DSF1
t CSH t RCD t RAD t RAH t RSH t CAS t RAL t ASC t CAH
SAM Start Address
t CRP
t ASR
LP
Row t WS t WH t DTS t DTH t FSR t RFH t SRS t SC t SIS t SIH
Valid Sin
High-Z t DTP t DRD
t SAH
t SDH t SCP t SC
t SCC t SCP t SCA t SOH Valid Sout
ro
t SCH t SRH t CQD t CQH
SC
Inhibit Rising Transition t SCA
SI/O (Output) SI/O (Input)
t SZS
t RQD t RQH QSF SAM Address MSB
t DQD
Data Sheet E0163H10 44
du
t DQH
ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input) QSF I/O (Input)
Masked Write Transfer Cycle
t RC t RAS t CSH t CAS t CAH t RP t CRP t RSH
t RCD t ASR t RAH t ASC
t SCA Valid t SOH
Note: 1. I/O mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode.
LP
Row t WS t WH t DTS t DTH t FSR t RFH t SRS t SC t SRZ Valid High-Z t CQH t RQD t RQH SAM Address MSB t MS t MH
I/O Mask Data *1
SAM Start Address
High-Z
t SRD t SCP
t SCC t SC t SCP
Inhibit Rising Transition t SID t SIS t SIH
Valid Sin
Data Sheet E0163H10 45
ro
t CQD
t SIS t SIH
Valid Sin
du ct
HM538253B/HM538254B Series
Split Read Transfer Cycle (HM538253B)
t RC t RAS t CSH t CRP t RCD t RSH t CAS t RAD t ASR t RAH t ASC t CAH t RAL SAM Start Address Yi t CRP t RP
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input)
Valid Sout
Bi *2
t SCA t SOH
t SQH
LP
Row
t WS t WH t OFF1 t DTS t DTH t FSR t RFH t STS t SC
High-Z
t SCC
ro
t AST t RST t SCP
t CST
Ym*1
Ym + 1
t SOH
Ym + 2
Bj - 2
Bj - 1
Bj *2
Yi
t SCA
Valid Sout
Valid Sout
Valid Sout
Valid Sout
Valid Sout
du
High-Z
t SQD
t SQD t SQH
QSF
SAM Address MSB
Notes: 1. Ym is the SAM start address in before SRT. 2. Bi, Bj initiate the boundary address. 3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set on the boundary address.
ct
Data Sheet E0163H10 46
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input) QSF I/O (Input)
Masked Split Write Transfer Cycle (HM538253B)
t RC t RAS t CSH t RSH t CAS t RP
t RCD t ASR t RAH Row
t ASC t CAH
SAM Start Address Yi
Valid Sin
t SQD t SQH
Notes: 1. Ym is the SAM start address in before MSWT. 2. Bi, Bj initiate the boundary address. 3. I/O Mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode. 4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set on the boundary address.
LP
t WS tWH t OFF1 t DTS t DTH t FSR t RFH t STS Bi*2 Ym*1 Ym+1 t SIS t SIH
Valid Sin Valid Sin
High-Z
t SCC t SC t SCP
ro
t RST Ym+2 t SIS t SIH
Valid Sin
t AST
t CST
Bj-2
Bj-1
Bj*2
Yi
SAM Address MSB t CDD t MS t MH
du
Valid Sin
t SIS t SIH
Valid Sin Valid Sin
t SQD t SQH
*3 I/O Mask Data
ct
Data Sheet E0163H10 47
HM538253B/HM538254B Series
Serial Read Cycle
SE
EO
SC SI/O (Output)
tSCC tSC tSCA tSOH tSCP tSC
tSCC tSCP tSC tSEA tSCA tSLZ
tSCC tSCP
tSC tSCA tSOH Valid Sout
Valid Sout
tSHZ Valid Sout
Valid Sout
LP
tSWH tSWIS tSCC tSC tSCP tSIS tSIH Valid Sin t RCD t ASR t RAD t RAH t ASC Row t DZC t DZO t DTS t DTH t RFH t FSC t FSR
Serial Write Cycle
tSWIH
tSWS
SE
tSCC tSCP tSC
tSCC tSCP tSC
tSC
SC SI/O (Input)
tSIS
tSIH
tSIS
tSIH
Valid Sin
Valid Sin
ro
t RC t RAS t CSH t RAL t CAH Column t RCS t CAC t AA t RAC t OAC t CFH
Read Cycle (HM538254B)
t RP t CRP
RAS
t RSH t CAS
du
t CAL t RRH t RHZ Valid Dout t RDD
CAS
Address
t RCH t CDD
WE
t CHZ
I/O (Output) I/O (Input)
t OFF2
ct
t ODD
DT/OE
DSF1
Data Sheet E0163H10 48
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 RAS CAS Address I/O (Output) I/O (Input) DT/OE DSF1
Hyper Page Mode Read Cycle (HM538254B)
t RC t RASP t CSH t CAS t RCD t RAD t ASR t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH Column t CP t RAL t ASC t CAL t CAH Column t RRH t AA t ACP t CAC
Valid Dout
t RP t RSH t CAS
t CRP
t ASC
RAS-Only Refresh Cycle (HM538254B)
LP
Column t RCS t RAC t AA t CAC t DZC t OAC t DTS t DZO t DTH t RFH t FSR t FSC t CFH t CRP t ASR t RAH Row t CHZ t CDD t OFF2 t ODD t DTS t FSR t DTH t RFH
t RCH
t AA t ACP t CAC
Valid Dout
t CHZ t RHZ t CDD t ODD
Valid Dout
t DOH
t DOH t RDD t OFF2
t FSC
t CFH
t FSC
t CFH
Data Sheet E0163H10 49
ro
t RAS
t RC t RP t RPC
du
ct
WE : H or L
HM538253B/HM538254B Series
CAS-Before-RAS Refresh Cycle (CBRN) (HM538254B)
t RC t RP t RPC t CP t RAS t RP t CSR
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
t CSR
t CHR
t RPC Inhibit Falling Transition
t WS
t WH
Hidden Refresh Cycle (HM538254B)
LP
t RHZ t CHZ t FSR t RC t RAS t RCD t RSH t ASR Row t RAD t RAL t RAH t ASC t CAH Column t RCS t CAC t AA t RAC t DZC t DZO t DTH t RFH t OAC t DTS t FSR t FSC t CFH
High-Z
t RFH
SC : H or L
Data Sheet E0163H10 50
ro
t RP t RRH t WS t FSR
t RC t RAS t RP t CRP
t CHR
t WH
du
Valid Dout t RFH
t CHZ t RHZ
t OFF2
ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1
Flash Write Cycle (HM538254B)
t RC t RAS t CRP t ASR Row t WS t WH t RCD t RAH t RP
t CHZ
t OFF2
LP
t CDD t ODD t MS t DTS t FSR
High-Z
t MH
Mask Data t DTH t RFH
Data Sheet E0163H10 51
ro du ct
HM538253B/HM538254B Series
Register Read Cycle (Mask data, Color data) (HM538254B)
t RC t RAS t CSH t CAS t RP t CRP t RSH
EO
RAS CAS Address WE I/O (Output) I/O (Input) DT/OE DSF1 52
t RCD t ASR t RAH
Note: 1. State of DFS1 at falling edge of CAS State Accessed data 0
LP
Row t WS t WH t RCS t RAC t DZC t DTS t FSR t DZO t DTH t RFH t FSC
*1
t RRH t CAC t RHZ Valid Out t OAC t OFF2 t ODD t RDD t CDD t CHZ
t RCH
Mask data (LMR)
t CFH
Data Sheet E0163H10
ro
1 Color data (LCR)
du ct
HM538253B/HM538254B Series
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input)
Valid Sout
Split Read Transfer Cycle (HM538254B)
t RC t RAS t CSH t CRP t RCD t RSH t CAS t RAD t ASR t RAH t ASC t CAH t RAL SAM Start Address Yi t CRP t RP
Bi *2
t SCA t SOH
t SQH
LP
Row
t WS t WH t CHZ t DTS t DTH t FSR t RFH t STS t SC
High-Z
t SCC
ro
t SCP
t CST t AST
t RST
Ym*1
Ym + 1
t SOH
Ym + 2
Bj - 2
Bj - 1
Bj *2
Yi
t SCA
Valid Sout
Valid Sout
Valid Sout
Valid Sout
Valid Sout
du
High-Z
t SQD
t SQD t SQH
QSF
SAM Address MSB
Notes: 1. Ym is the SAM start address in before SRT. 2. Bi, Bj initiate the boundary address. 3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't on the boundary address.
ct
53
Data Sheet E0163H10
HM538253B/HM538254B Series
Masked Split Write Transfer Cycle (HM538254B)
t RC t RAS t CSH t RSH t CAS t RP
EO
RAS CAS Address WE I/O (Output) DT/OE DSF1 SC SI/O (Output) SI/O (Input) QSF I/O (Input) 54
t RCD t ASR t RAH Row
t ASC t CAH
SAM Start Address Yi
Valid Sin
t SQH
Notes: 1. Ym is the SAM start address in before MSWT. 2. Bi, Bj initiate the boundary address. 3. I/O Mask data (In new mask mode) Low: Mask High: Non mask I/O: H or L in persistent mask mode. 4. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit. SAM start address can't set or the boundary address.
LP
t WS tWH t CHZ t DTS t DTH t FSR t RFH t STS Bi*2 Ym*1 Ym+1 t SIS t SQD t SIH
Valid Sin
Invalid Dout
High-Z
t SCC t SC t SCP
ro
t RST Ym+2 t SIS t SIH
Valid Sin
t AST
t CST
Bj-2
Bj-1
Bj*2
Yi
du
Valid Sin
t SIS t SIH
Valid Sin Valid Sin
Valid Sin
t SQD t SQH
SAM Address MSB t CDD t MS t MH
*3 I/O Mask Data
ct
Data Sheet E0163H10
HM538253B/HM538254B Series
10.16 0.13
0.74
3.50 0.26
1
20
11.18 0.13
1.30 Max
0.43 0.10
1.27
0.80
9.40 0.25
0.10
HM538253BTT/HM538254BTT Series (TTP-44/40DA)
18.41 18.81 Max 35 32
0.31 2.30 + 0.14 -
+0.25 -0.17
1
10 13 0.80 0.21 M 1.005 Max 2.40 0.10
22
0.30 0.10
10.16
1.20 Max
0.17 0.05
0.13 0.05
EO
Package Dimensions
HM538253BJ/HM538254BJ Series (CP-40D)
25.80 26.16 Max 21
Unit: mm
40
LP
44 23
Data Sheet E0163H10 55
ro du
11.76 0.20 0.80 0.50 0.10
Unit: mm
ct
0 - 5
HM538253B/HM538254B Series
Cautions
EO
56
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
LP
Data Sheet E0163H10
ro
du ct

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